参照ISO/IEC 18000-6 Type B协议设计了一款工作频率为915 MHz的射频读卡器,采用FPGA完成协议中规定的数字信号处理,C8051F020单片机作为主控器。利用Verilog HDL硬件描述语言,搭建FPGA内部各个小模块及系统的验证平台,选用Altera公司Cy...参照ISO/IEC 18000-6 Type B协议设计了一款工作频率为915 MHz的射频读卡器,采用FPGA完成协议中规定的数字信号处理,C8051F020单片机作为主控器。利用Verilog HDL硬件描述语言,搭建FPGA内部各个小模块及系统的验证平台,选用Altera公司Cyclone系列的EP1C6Q240C8芯片为目标器件,使用Quartus Ⅱ进行综合,并通过时序和功能验证。实验结果表明,该读卡器符合ISO/IEC 18000-6 Type B协议要求,具有结构灵活、体积小、升级容易等优点。展开更多
By means of a Monte Carlo simulation,we study the three-state Potts model on a two-dimensional quasiperiodic structure based on a dodecagonal cluster covering pattern.The critical temperature and exponents are obtaine...By means of a Monte Carlo simulation,we study the three-state Potts model on a two-dimensional quasiperiodic structure based on a dodecagonal cluster covering pattern.The critical temperature and exponents are obtained from finite-size scaling analysis.It is shown that the Potts model on the quasiperiodic lattice belongs to the same universal class as those on periodic ones.展开更多
文摘参照ISO/IEC 18000-6 Type B协议设计了一款工作频率为915 MHz的射频读卡器,采用FPGA完成协议中规定的数字信号处理,C8051F020单片机作为主控器。利用Verilog HDL硬件描述语言,搭建FPGA内部各个小模块及系统的验证平台,选用Altera公司Cyclone系列的EP1C6Q240C8芯片为目标器件,使用Quartus Ⅱ进行综合,并通过时序和功能验证。实验结果表明,该读卡器符合ISO/IEC 18000-6 Type B协议要求,具有结构灵活、体积小、升级容易等优点。
基金Supported by the National Natural Science Foundation of China under Grant No 10474021.
文摘By means of a Monte Carlo simulation,we study the three-state Potts model on a two-dimensional quasiperiodic structure based on a dodecagonal cluster covering pattern.The critical temperature and exponents are obtained from finite-size scaling analysis.It is shown that the Potts model on the quasiperiodic lattice belongs to the same universal class as those on periodic ones.
