Developing low-power FETs holds significant importance in advancing logic circuits,especially as the feature size of MOSFETs approaches sub-10 nanometers.However,this has been restricted by the thermionic limitation o...Developing low-power FETs holds significant importance in advancing logic circuits,especially as the feature size of MOSFETs approaches sub-10 nanometers.However,this has been restricted by the thermionic limitation of SS,which is limited to 60 mV per decade at room temperature.Herein,we proposed a strategy that utilizes 2D semiconductors with an isolated-band feature as channels to realize subthermionic SS in MOSFETs.Through high-throughput calculations,we established a guiding principle that combines the atomic structure and orbital interaction to identify their sub-thermionic transport potential.This guides us to screen 192 candidates from the 2D material database comprising 1608 systems.Additionally,the physical relationship between the sub-thermionic transport performances and electronic structures is further revealed,which enables us to predict 15 systems with promising device performances for low-power applications with supply voltage below 0.5 V.This work opens a new way for the low-power electronics based on 2D materials and would inspire extensive interests in the experimental exploration of intrinsic steep-slope MOSFETs.展开更多
基金supported by the Postgraduate Research&Practice Innovation Program of Jiangsu Province(KYCX22_0428)the Training Program of the Major Research Plan of the National Natural Science Foundation of China(91964103)+3 种基金the Natural Science Foundation of Jiangsu Province(BK20180071)the Fundamental Research Funds for the Central Universities(30919011109)sponsored by Qing Lan Project of Jiangsu Province,and the Six Talent Peaks Project of Jiangsu Province(XCL-035)Research Grant Council of Hong Kong(CRS_PolyU502/22).
文摘Developing low-power FETs holds significant importance in advancing logic circuits,especially as the feature size of MOSFETs approaches sub-10 nanometers.However,this has been restricted by the thermionic limitation of SS,which is limited to 60 mV per decade at room temperature.Herein,we proposed a strategy that utilizes 2D semiconductors with an isolated-band feature as channels to realize subthermionic SS in MOSFETs.Through high-throughput calculations,we established a guiding principle that combines the atomic structure and orbital interaction to identify their sub-thermionic transport potential.This guides us to screen 192 candidates from the 2D material database comprising 1608 systems.Additionally,the physical relationship between the sub-thermionic transport performances and electronic structures is further revealed,which enables us to predict 15 systems with promising device performances for low-power applications with supply voltage below 0.5 V.This work opens a new way for the low-power electronics based on 2D materials and would inspire extensive interests in the experimental exploration of intrinsic steep-slope MOSFETs.
