Using standard 0.18-μm CMOS process and the special platform for S-inch phase change random access memory （PCRAM）, the first Chinese 16k bits PCRAM chip has been successfully achieved. A 1RIT structure has been des...Using standard 0.18-μm CMOS process and the special platform for S-inch phase change random access memory （PCRAM）, the first Chinese 16k bits PCRAM chip has been successfully achieved. A 1RIT structure has been designed for low voltage drop and low cost compared to the 1RlD structure and the BJT-switch structure. Full integration of the 16k bits PCRAM chip, including memory cell, array structure, critical circuit module, and physical layout, has been designed and verified. The critical integration technology of the phase change material （PCM） fabrication and the standard CMOS process has been solved. Test results about PCM in a large-scale array have been generated for the next research of PCRAM chip.展开更多
A low ripple switched capacitor charge pump applicable to phase change memory （PCM） is presented. For high power efficiency, the selected charge pump topology can automatically change the power conversion ratio betw...A low ripple switched capacitor charge pump applicable to phase change memory （PCM） is presented. For high power efficiency, the selected charge pump topology can automatically change the power conversion ratio between 2X/1.5X modes with the input voltage. For a low output ripple, a novel operation mode is used. Compared with the conventional switched capacitor charge pump, the flying capacitor of the proposed charge pump is charged to Vo- 14n during the charge phase （Vo is the prospective output voltage）. In the discharge phase, the flying capacitor is placed in series with the Vin to transfer energy to the output, so the output voltage is regulated at Vo. A simulation was implemented for a DC input range of 1.6-2.1 V in on SMIC standard 40 nm CMOS process, the result shows that the new operation mode could regulate the output of about 2.5 V with a load condition from 0 to 10 mA, and the ripple voltage is lower than 4 mV. The maximum power efficiency reaches 91%.展开更多
基金Supported by the National Basic Research Programme of China under Nos 2007CB935400 and 2006CB302700, the National High-Technology Research and Development Programme of China under Grant Nos 2008AA031402 and 2006AA03Z360, the Science and Technology Council of Shanghai under Grant Nos 0752nm013, 07QA14065 and 07SA08, and National Nature Science Foundation of China under Grant No 60776058.
文摘Using standard 0.18-μm CMOS process and the special platform for S-inch phase change random access memory （PCRAM）, the first Chinese 16k bits PCRAM chip has been successfully achieved. A 1RIT structure has been designed for low voltage drop and low cost compared to the 1RlD structure and the BJT-switch structure. Full integration of the 16k bits PCRAM chip, including memory cell, array structure, critical circuit module, and physical layout, has been designed and verified. The critical integration technology of the phase change material （PCM） fabrication and the standard CMOS process has been solved. Test results about PCM in a large-scale array have been generated for the next research of PCRAM chip.
基金supported by the National Key Basic Research Program of China(Nos.2010CB934300,2011CBA00607,2011CB932800)the National Integrated Circuit Research Program of China(No.2009ZX02023-003)+1 种基金the National Natural Science Foundation of China(Nos. 60906004,60906003,61006087,61076121)the Science and Technology Council of Shanghai(No.1052nm07000)
文摘A low ripple switched capacitor charge pump applicable to phase change memory （PCM） is presented. For high power efficiency, the selected charge pump topology can automatically change the power conversion ratio between 2X/1.5X modes with the input voltage. For a low output ripple, a novel operation mode is used. Compared with the conventional switched capacitor charge pump, the flying capacitor of the proposed charge pump is charged to Vo- 14n during the charge phase （Vo is the prospective output voltage）. In the discharge phase, the flying capacitor is placed in series with the Vin to transfer energy to the output, so the output voltage is regulated at Vo. A simulation was implemented for a DC input range of 1.6-2.1 V in on SMIC standard 40 nm CMOS process, the result shows that the new operation mode could regulate the output of about 2.5 V with a load condition from 0 to 10 mA, and the ripple voltage is lower than 4 mV. The maximum power efficiency reaches 91%.
