微系统芯片(System-on-Chip,SoC)发展到今天,集成密度指数增长和芯片面积的急剧膨胀使得全局连线的延时上升,可靠性下降,成为集成电路的设计瓶颈.片上网络(Network-on-Chip,NoC)是解决整个芯片上数据有效传输的结构之一,以片上网络为基...微系统芯片(System-on-Chip,SoC)发展到今天,集成密度指数增长和芯片面积的急剧膨胀使得全局连线的延时上升,可靠性下降,成为集成电路的设计瓶颈.片上网络(Network-on-Chip,NoC)是解决整个芯片上数据有效传输的结构之一,以片上网络为基础通信架构的微系统芯片称为片上网上系统芯片(System-on-Network-on-Chip,SoNoC).微系统芯片内通信模式兼有随机性和确定性,应该根据特定应用的通信特征设计片上网络.本文在确定SoNoC设计流程的基础上,根据SoNoC的通信特征,选择了合适的离散平面结构,对SoNoC的运算及控制等模块进行布局、对模块间的通信依赖关系进行布线,发展出FRoD(Floor-plan and Routing on Discrete Plane)算法,以自动生成片上网络的拓扑结构.该算法定义了离散平面的一般表示方法,并在四种典型的离散平面上使用不同规模的随机系统完成了系列实验.为了处理系统和网络之间的耦合关系,逐点分裂的布局算法可以逐步学习和适应系统的通信需求,同时优化系统的执行时间和通信能量,在运行随机任务流图的模拟系统上与随机布局结果相比可以节省30%左右的通信能量,20%左右的系统通信时间.串行、并行和串并混合的布线算法使用最短路径把通信关系分布在离散平面的通道上,使不同的通信关系尽量复用网络通道,与全连接网络相比可以节省10%到30%的面积代价.展开更多
A full on-chip and area-efficient low-dropout linear regulator （LDO） is presented. By using the proposed adaptive frequency compensation （AFC） technique, full on-chip integration is achieved without compromising t...A full on-chip and area-efficient low-dropout linear regulator （LDO） is presented. By using the proposed adaptive frequency compensation （AFC） technique, full on-chip integration is achieved without compromising the LDO＇s stability in the full output current range. Meanwhile, the use of a compact pass transistor （the compact pass transistor serves as the gain fast roll-off output stage in the AFC technique） has enabled the LDO to be very areaefficient. The proposed LDO is implemented in standard 0.35 μm CMOS technology and occupies an active area as small as 220 × 320/zm^2, which is a reduction to 58% compared to state-of-the-art designs using technologies with the same feature size. Measurement results show that the LDO can deliver 0-60 mA output current with 54 μA quiescent current consumption and the regulated output voltage is 1.8 V with an input voltage range from 2 to 3.3 V.展开更多
文摘微系统芯片(System-on-Chip,SoC)发展到今天,集成密度指数增长和芯片面积的急剧膨胀使得全局连线的延时上升,可靠性下降,成为集成电路的设计瓶颈.片上网络(Network-on-Chip,NoC)是解决整个芯片上数据有效传输的结构之一,以片上网络为基础通信架构的微系统芯片称为片上网上系统芯片(System-on-Network-on-Chip,SoNoC).微系统芯片内通信模式兼有随机性和确定性,应该根据特定应用的通信特征设计片上网络.本文在确定SoNoC设计流程的基础上,根据SoNoC的通信特征,选择了合适的离散平面结构,对SoNoC的运算及控制等模块进行布局、对模块间的通信依赖关系进行布线,发展出FRoD(Floor-plan and Routing on Discrete Plane)算法,以自动生成片上网络的拓扑结构.该算法定义了离散平面的一般表示方法,并在四种典型的离散平面上使用不同规模的随机系统完成了系列实验.为了处理系统和网络之间的耦合关系,逐点分裂的布局算法可以逐步学习和适应系统的通信需求,同时优化系统的执行时间和通信能量,在运行随机任务流图的模拟系统上与随机布局结果相比可以节省30%左右的通信能量,20%左右的系统通信时间.串行、并行和串并混合的布线算法使用最短路径把通信关系分布在离散平面的通道上,使不同的通信关系尽量复用网络通道,与全连接网络相比可以节省10%到30%的面积代价.
基金supported by Shanghai-Applied Material Research Development Fund(No.09700714100).
文摘A full on-chip and area-efficient low-dropout linear regulator （LDO） is presented. By using the proposed adaptive frequency compensation （AFC） technique, full on-chip integration is achieved without compromising the LDO＇s stability in the full output current range. Meanwhile, the use of a compact pass transistor （the compact pass transistor serves as the gain fast roll-off output stage in the AFC technique） has enabled the LDO to be very areaefficient. The proposed LDO is implemented in standard 0.35 μm CMOS technology and occupies an active area as small as 220 × 320/zm^2, which is a reduction to 58% compared to state-of-the-art designs using technologies with the same feature size. Measurement results show that the LDO can deliver 0-60 mA output current with 54 μA quiescent current consumption and the regulated output voltage is 1.8 V with an input voltage range from 2 to 3.3 V.
