摘要
集成电路的测试变得日益重要,传统的门级测试虽然效果很好,但是随着电路规模的增大而面临着测试时间太长的困境·高层测试可以很好地缓解测试时间过长的问题,但最大的困难是缺少恰当的故障模型·通过对高层故障模型与门级固定型故障模型间关系可以建立高层故障模型的评估规则,在该规则下可以再对高层故障模型间关系进行分析,以确定彼此间的覆盖关系·归纳模型间的互相覆盖以确定彼此是否包含,这有助于对高层故障模型进行评估,寻找能够对应逼近门级固定型(stuck-at)故障模型的高层故障模型序列,该模型序列有望指导新的测试生成·最后,以对ITC99中标准时序电路的实验来说明该理论方法·
With the development of integrated circuit design, the traditional test done at gate level is proved to be time-consuming. It＇s necessary to test circuit at high level. Unfortunately, there are no effective fault models defined at high level, To solve this problem, two kinds of relationships between different fault models are analyzed. The relationship between a high level fault model and the stuck-at fault model（defined at gate level） is analyzed, followed by the analysis of relationship between two high level fault models. These relationships are expected to found one or a set of effective high-level fault models. High-level fault models founded are expected to direct ATPG（automatie test pattern generation） and DFT（design for test） more effectively than traditional ones. Two rules are defined to evaluate the high-level fault models. The induction is used to find these relationships in theory. According to the method presented, if test patterns generated by one high-level fault model can detect more detectable stuck-at fault models defined at gate level than other fault models, it is proved to be more effective. The experiment conducted on benchmark of ITC99 demonstrates this approach. Three kinds of high-level fault models are analyzed, which are the transfer fault model, the states fault model, and the branch fault model.
出处
《计算机研究与发展》
EI
CSCD
北大核心
2006年第2期350-355,共6页
Journal of Computer Research and Development
基金
国家自然科学基金项目(90207002
60242001)
中国科学院计算技术研究所基础研究基金项目(20036160)~~
