摘要
研究了DVB-S2标准LDPC码编译码器的硬件结构,以16 200码长和0.6码率为例设计了基于共享内存和后验概率累加储存的译码器结构,不仅吞吐量大,而且寄存器和内存资源的消耗小。仿真分析了同码长不同码率和同码率不同码长的性能,当码长相等时,码率越低,则误码率、误帧率和平均迭代次数一般均越低。同码率不同码长的码组,虽然校验位和信息位的比例相等,但是码长越大,校验位和信息位的约束更强,性能越好。
The hardware architecture of the DVB-S2 LDPC code encoder and decoder is researched. Decoder with code rate 0.6 and code length 16 200 by using shared memory banks and writing the LLR （Log-Likelihood Ratio） back to the RAM. This structure has low area and high throughput. Simulation result shows the analysis performance of the same code length with different code rate and the same code rate with different code length. When the code length is same, the lower the rate is, the error rate, frame error rate and average number of iteration are lower. The code words of the same code rate but different code length have equal bits proportion of the parity and information bits. But the longer the code length is the stronger the constraint between parity bit and information bit is, the longer the code length is the better the performance is.
出处
《电视技术》
北大核心
2012年第3期1-3,10,共4页
Video Engineering
基金
国家质检总局科技计划项目(2009QK027)
浙江省科技计划优先主题重点工业项目(2010C11024)
杭州市经济开发区产学研合作项目(201002)
